1. Field of the Invention
The present invention relates to a switching regulator, and more particularly, to a switching regulator capable of raising system stability by virtual ripple.
2. Description of the Prior Art
Regulators usually include switching regulators and liner regulators. The characteristics of liner regulators are that they are cheap, easy to use and respond quickly. However the efficiency of liner regulators is poor, often consuming 50% of the power. Although a switching regulator has slow response, its power efficiency is great. Power consumption plays an important role in circuit design nowadays. As for a quick response requirement, switching regulators utilize a constant-time trigger to substitute for an error amplifier with additional frequency compensation elements used for controlling signal differences between PWM loops. The constant-time trigger is used for triggering a fixed on time or a fixed off time to control the whole switching regulator.
Please refer to FIG. 1. FIG. 1 is a diagram of a switching regulator 10 according to the prior art. The switching regulator 10 includes a power stage 12, an output capacitor Cout, a loading Rload, a reference voltage generator 14, a comparator 15, and a constant-time trigger 16. The power stage 12 includes a first switch SW1, a second switch SW2, an inverter 17, and an output inductor Lout. The second switch SW2 is coupled to the first switch SW1. The output inductor Lout is coupled to the first switch SW1 and the second switch SW2. The inverter 17 is coupled to the constant-time trigger 16 and a control end 104 of the second switch SW2 for processing an inverse operation on a signal outputted from the constant-time trigger 16. The output capacitor Cout is coupled to the output inductor Lout with an output voltage Vout across the capacitor. The output capacitor Cout further includes an equivalent series resistance ESR. The reference voltage generator 14 is used for generating a reference voltage Vref. The comparator 15 includes a first input end 152 coupled to the output inductor Lout and the output capacitor Cout for receiving a feedback voltage VFB (equals the output voltage Vout). The comparator 15 includes a second input end 154 coupled to the reference voltage generator 14. The constant-time trigger 16 is coupled to the comparator 15 and the power stage 12. The constant-time trigger 16 is used for controlling turning on and off the first switch SW1 and the second switch SW2 of the power stage 12 according to a result of the comparator 15. The comparator 15 is an error comparator. The first switch SW1 and the second switch SW2 are metal-oxide semiconductor transistors (MOS). When the constant-time trigger 16 is an on-time trigger, it is used for controlling on time of the first switch SW1 and the second switch SW2. When the constant-time trigger 16 is an off-time trigger, it is used for controlling off time of the first switch SW1 and the second switch SW2.
Please refer to FIG. 2 and FIG. 1. FIG. 2 is a diagram illustrating signal waveforms in FIG. 1. The upper waveform is a variation of an inductor current IL in time, where it rises in a positive slope for a span and drops in a negative slope for a span. Due to the output voltage Vout equaling the feedback voltage VFB, the feedback voltage VFB could be represented as the product of the inductor current IL and the equivalent series resistance ESR. Assume that the constant-time trigger 16 is an on time trigger for controlling turning on the first switch SW1 for a fixed time T1. The comparator 15 is used for comparing the feedback voltage VFB and the reference voltage Vref. When the feedback voltage VFB is lower than the reference voltage Vref, the comparator 15 triggers a high level signal to the constant-time trigger 16. The constant-time trigger 16 controls the first switch SW1 turning on for the fixed time T1 and turning off the first switch SW1. The constant-time trigger 16 turns on the second switch SW2 to form a loop.
Please refer to FIG. 3. FIG. 3 is a diagram of a switching regulator 30 according to the prior art. The switching regulator 30 includes a power stage 12, an output capacitor Cout, a loading Rload, a first reference voltage generator 32, a second reference voltage generator 34, a selector 38, and a comparator 35. The power stage 12 includes a first switch SW1, a second switch SW2, an inverter 17, and an output inductor Lout and is the same as the power stage 12 in FIG. 1. The output capacitor Cout is coupled to the output inductor Lout with an output voltage Vout across the capacitor. The output capacitor Cout further includes an equivalent series resistance ESR. The loading Rload is coupled to the output capacitor Cout and the output inductor Lout. The first reference voltage generator 32 is used for generating a first reference voltage Vref1. The second reference voltage generator 34 is used for generating a second reference voltage Vref2. The comparator 35 includes a first input end 352 coupled to the output inductor Lout and the output capacitor Cout for receiving a feedback voltage VFB (equals the output voltage Vout). The comparator 35 includes a second input end 354 coupled to an output end 386 of the selector 38. The selector 38 includes a first input end 382 coupled to the first reference voltage generator 32 for receiving the first reference voltage Vref1, and a second input end 384 coupled to the second reference voltage generator 34 for receiving the second reference voltage Vref2. The selector 38 is used for selecting the first reference voltage Vref1 or the second reference voltage Vref2 to enter the second input end 354 of the comparator 35. The comparator 35 is a hysteresis comparator and is used for comparing the output voltage Vout with the first reference voltage Vref1 or the second reference voltage Vref2. The output of the comparator 35 is used for controlling turning on and off the first switch SW1 and the second SW2 of the power stage 12. The first switch SW1 and the second switch SW2 are metal-oxide semiconductor transistors (MOS).
Please refer to FIG. 4 and FIG. 3. FIG. 4 is a diagram illustrating signal waveforms in FIG. 3. The difference between FIG. 4 and FIG. 2 is that the comparator 35 is a hysteresis comparator. The first input end 352 of the comparator 35 is used for receiving the feedback voltage VFB, and the second input end 354 of the comparator 35 is used for receiving the first reference voltage Vref1 or the second reference voltage Vref2. When the feedback voltage VFB is smaller than the second reference voltage Vref2, the comparator 35 triggers a high level signal to turn on the first switch SW1. When the feedback voltage VFB is greater than the first reference voltage Vref1, the comparator 35 triggers a low level signal to turn off the first switch SW1 to form a loop.
Virtual ripple applications are already disclosed in U.S. Pat. No. 6,583,610“Virtual Ripple generation in Switch-mode power Supplies” and U.S. Pat. No. 6,813,173“DC-to-DC Converter with Improved Transient Response”. In U.S. Pat. No. 6,583,610, the method of work is adding a triangle-like wave signal to the feedback side to differentiate the variation of the feedback voltage and improve the discrimination of the comparator. In U.S. Pat. No. 6,813,173, the method of work is adding a signal equaling the product of the inductor current IL and the equivalent series resistance ESR to simulate the waveform of the feedback voltage applied in large equivalent series resistance.
Due to the equivalent series resistance ESR of the output capacitor Cout used in today's switching regulator being small, such as MLCC capacitors, there is phase difference generated in the feedback voltage VFB that causes system instability.